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HV57708 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs
Features
HVCMOS(R) technology 5.0V CMS Logic Output voltage up to +80V Low power level shifting 32MHz equivalent data rate Latched data outputs Foreward and reverse shifting options (DIR pin) Diode to VPP allows efficient power recovery Outputs may be hot switched
General Description
The device has 4 parallel 16-bit registers, permitting data rates 4x the speed of one (they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE input is high. The data in the latches is stored when the LE is low.
General Description
The HV57708 is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays.
Functional Block Diagram
DO 1 DO 2 D I4 D I3 DO 3 D O4 D I2 D I1 V DD LE BL POL V PP
DIR SR1
HVOUT 1 5 9 * * * HVOUT61
SR2
HVOUT 2 6 10 * * * HVOUT62
CLK HVOUT 3 7 11 * * * HVOUT63
SR3
SR4
HVOUT 4 8 12 * * * HVOUT64
Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc.
D O4 D O3 DI 1 DI 2
D O2 DI 3
D O1 DI 4
GND
HV57708
Ordering Information
Device HV57708 Package Options 80-Lead PQFP HV57708PG-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter Supply voltage, VDD Output voltage , VPP Logic input levels Ground current(1) Continuous total power dissipation(2) Operating temperature range Storage temperature range Lead temperature 1.6mm from case for 10 seconds Value -0.5V to +7.5V -0.5V to +90V -0.3V to VDD + 0.3V 1.5A 1200mW -40C to +85C -65C to +150C 260C
Pin Configuration
80 1
80-Lead PQFP (PG)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Limited by the total dissipated in the package. 2. For operation above 25C ambient derate linearly to maximum operating temperature at 20mW/C.
Product Marking
Top Marking
YYWW
HV57708PG
LLLLLLLLLL
Bottom Marking
CCCCCCCC AAA
YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging
*May be part of top marking
80-Lead PQFP (PG)
Recommended Operating Conditions
Symbol VDD VPP VIH VIL fCLK TA Parameter Logic supply voltage Output voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Min 4.5 8.0 VDD - 0.5V 0 -40 Max 5.5 80 0.5 8.0 +85 Units V V V V MHz C
Notes: Power-up sequence should be the following*: 1. Apply ground 2. Apply VDD 3. Set all inputs (DIN, CLK, LE , POL, etc.) to a known state 4. Apply VPP 5. The VPP should not drop below VDD or float during operation Power-down sequence should be the reverse of the above
2
HV57708
DC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted)
Symbol IDD IPP IDDQ VOH VOL IIH IIL VOC Parameter VDD supply current High voltage supply current Quiescent VDD supply current High level output HVOUT DOUT HVOUT DOUT Min 65 VDD - 0.5V A
Max 15 100 100 100 7.0 0.5 1.0 -1.0 1.0
Units mA A A A V V V V A A V
Conditions VDD = VDD max, fCLK = 8MHz Outputs high Outputs low All VIN = VDD IO = -15mA, VPP = +80V IO = -100A IO = 12mA, VPP = +80V IO = 100A VIH = VDD VIL = 0V IOC = 1.0mA
Low level output
High-level logic input current Low-level logic input current High voltage clamp diode
AC Electrical Characteristics (T
Symbol fCLK tWL, tWH tSU tH tON, tOFF tDHL tDLH tDLE* tWLE tSLE Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable to HVOUT
= 85C max. Logic signal inputs and Data inputs have tr, tf 5ns [10% and 90% points])
Min 62 10 15 25 25 0
Max 8 500 70 70 -
Units MHz ns ns ns ns ns ns ns ns ns
Conditions Per register ------CL = 15pF CL = 15pF CL = 15pF -------
Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high LE pulse width LE set-up time before clock rises
* tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
3
HV57708
Input and Output Equivalent Circuits
V DD V DD V PP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
GND High Voltage Outputs
Switching Waveforms
VIH Data Input 50% tSU Clock 50% tWL 50% tWH VOH 50% VOL Data Out tDLH VOH 50% VOL tDHL VIH Latch Enable tDLE 50% tWLE 50% VOL tSLE VOH VOL Data Valid tH 90% 50% 50% VIL tf tr VIH 10% 10% 90% 50% VIL
HVOUT w/ S/R LOW tOFF HVOUT w/ S/R HIGH
90% 10%
10% tON
90%
VOH VOL
4
HV57708
Function Table
Inputs Function Data X X X X L H L H X X DI/O1-4A I/O relation DI/O1-4A DI/O1-4B DI/O1-4B
Note: * = data at the last CLK
Outputs BL L L H H H H H H H H H H H H POL L H H L H H L L H L H H H H DIR X X X X X X X X X X H H L L Shift Reg L H L H * * QnQn+1 QnQn+1 QnQn-1 QnQn-1 HV Outputs H L No inversion Inversion L H H L Stored Data Inversion of stored data New H or L Previous H or L Previous H or L New H or L Data Out DI/O1-4B DI/O1-4B DI/O1-4A DI/O1-4A
CLK X X X X _ _ _ _ _ _ _ _ X X _ _ _ _ _ _ _ _
LE X X X X H H H H L L H L L H
All O/P high All O/P low O/P normal O/P inverted Data falls through (latches transparent)
Data stored/ latches loaded
Shift Register Operation
HV OUT 32 DIR = H; CW (HVOUT1 HVOUT64) DIR = L; CCW (HVOUT64 HVOUT1) * DIR = H * 1 * 2 * 3 * 4 HV OUT 2 HV OUT 1 Pin 25 26 27 28 36 37 38 39 SR4 1 HOUT 63 HOUT 64 SR3 2 * SR2 3 * SR1 4 * DIR = L * * HOUT 33
5
HV57708
Pin Function
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function HVOUT24/41 HVOUT23/42 HVOUT22/43 HVOUT21/44 HVOUT20/45 HVOUT29/46 HVOUT18/47 HVOUT17/48 HVOUT16/49 HVOUT15/50 HVOUT14/51 HVOUT13/52 HVOUT12/53 HVOUT11/54 HVOUT10/55 HVOUT9/56 HVOUT8/57 HVOUT7/58 HVOUT6/59 HVOUT5/60 Pin # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 37 39 40 Function HVOUT4/61 HVOUT3/62 HVOUT2/63 HVOUT1/64 DIN1/DOUT4(A) DIN2/DOUT3(A) DIN3/DOUT2(A) DIN4/DOUT1(A) LE CLK BL VDD DIR GND POL DOUT4/DIN1(B) DOUT3/DIN2(B) DOUT2/DIN3(B) DOUT1/DIN4(B) VPP Pin # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Function HVOUT64/1 HVOUT63/2 HVOUT62/3 HVOUT61/4 HVOUT60/5 HVOUT59/6 HVOUT58/7 HVOUT57/8 HVOUT56/9 HVOUT55/10 HVOUT54/11 HVOUT53/12 HVOUT52/13 HVOUT51/14 HVOUT50/15 HVOUT49/16 HVOUT48/17 HVOUT47/18 HVOUT46/19 HVOUT45/20 Pin # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT44/21 HVOUT43/22 HVOUT42/23 HVOUT41/24 HVOUT40/25 HVOUT39/26 HVOUT38/27 HVOUT37/28 HVOUT36/29 HVOUT35/30 HVOUT34/31 HVOUT33/32 HVOUT32/33 HVOUT31/34 HVOUT30/35 HVOUT29/36 HVOUT28/37 HVOUT27/38 HVOUT26/39 HVOUT25/40
Note: Pin designation for DIR = H/L. Example: For DIR = H, pin 41 is HVOUT64. For DIR = L, pin 41 is HVOUT1. For CW/CCW Shift see function table QN QN+1.
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HV57708
80-Lead PQFP Package Outline (PG)
20x14mm body, 0.80mm pitch
D D1
1 E E1
Note 1 (Index Area D1/4 x E1/4)
L2
80
Gauge Plane
1
e
b
L L1
Seating Plane
Top View View B
A A2 A1
Seating Plane
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 2.80 3.40
A1 0.25 -
A2 2.55 2.80 3.05
b 0.30 0.45
D 23.65 23.90 24.15
D1 19.80 20.00 20.20
E 17.65 17.90 18.15
E1 13.80 14.00 14.20
e 0.80 BSC
L 0.73 0.88 1.03
L1 1.95 REF
L2 0.25 BSC
0O 3.5 7
O O
1 5O 16O
JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV57708 A083107 7

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